1. Field of the Invention
This invention relates to a semiconductor logic integrated circuit composed of junction gate field-effect transistors.
2. Description of the Related Art
GaAs logic integrated circuits are attracting attention because of their high speed operation and low power consumption, and now undergo vigorous developments for higher speed and much larger-scale integration. Various types of basic circuits of GaAs logic integrated circuits have been proposed. Among them, direct-coupled FET logic (DCFL) circuits are widely used particularly for purposes of higher integration. DCFL circuits have advantages of low power consumption, operation on a single power supply, and high packing density.
FIG. 1A shows a DCFL 2-input NOR circuit. This circuit is made up of switching elements EFET.sub.1 and EFET.sub.2 of normally-off MESFETs, and a load element DFET of a normally-on MESFET. The DFET, whose gate and source are connected to each other, acts as a constant-current load. The gates of EFET.sub.1 and EFET.sub.2 are signal input terminals IN.sub.1 and IN.sub.2, respectively. When one of input terminals IN.sub.1 or IN.sub.2 goes to a high (Hi) level, the output terminal OUT drops to a low (Lo) level. When both input terminals IN.sub.1 and IN.sub.2 are at the Lo level, a Hi level output appears at the output terminal OUT.
The above DCFL circuit, which is of a simple arrangement with a small number of elements, has the following disadvantages:
(1) The noise margin is small because the logic amplitude is small. The reason for this is that since the gate electrode of a GaAs MESFET is of a Schottky junction, current flows between the gate and source of the next stage during the Hi level output, which clamps the Hi level output at the forward-direction rising voltage (normally, 0.6 to 0.8 V) at the Schottky junction. Therefore, the DCFL circuit is liable to be affected to fluctuations in the threshold value (V.sub.th) due to process variations, making it difficult to achieve a high yield stably.
(2) The load driving capability is low. The reason for this is that since, to obtain a sufficiently low level output, the current capacity of the DFET cannot be made very large, it takes time to charge the output from the Lo level to the Hi level when the output terminal OUT is connected to a heavy load. As a result, the switching speed becomes low.
(3) The logical capability is low. The logical capability shows how many logical functions can be realized with a single logic gate. The higher the logical capability, the smaller the number of gates used to realize a complex logic circuit. This helps to achieve low power consumption and high speed operation. Because the DCFL circuit has a small logic amplitude as noted earlier, the threshold value of an E-type FET used as a switching element is set nearly equal to the Lo level of the DCFL gate. Even when the gate voltage is the threshold voltage, however, the FET cannot cut off the drain current completely, carrying a very small current. This current is what is called a subthreshold current. For this reason, when the number of inputs increases in composing a DCFL NOR gate, current from the constant-current load flows through the E-type FET that should have been off. Consequently, as the number of NOR inputs increases, the Hi level drops accordingly. Because of this, in the DCFL circuit, the maximum number of inputs to the NOR circuit is limited to approximately 4 to 5. To realize a NOR logic with the number of inputs larger than 5, it is necessary to connect logic gates in multiple stages.
To eliminate such disadvantages, various circuits have been proposed.
FIG. 1B shows a DCFL circuit added with a push-pull buffer (hereinafter, simply referred to as a buffer), which is called a supper buffer FET logic (SBFL) circuit. This circuit enables a high speed operation, since two E-type FETs constituting the buffer stage rapidly charge the load capacitance at the output terminal. In contrast, during the Hi level output, the pull-up FET at the upper part of the buffer stage carries a large current, resulting in nearly three times as much power consumption as that of the basic DCFL circuit. The noise margin of this circuit is improved a little, but almost equals that of the basic DCFL circuit. Further, the disadvantage of a low logical capability is not improved very much with this circuit.
FIG. 1C shows a circuit in which a source follower buffer is added to the output stage of the DCFL circuit. By parallel-connecting E-type FETs at the upper part of the source flower stage in the circuit, what is called wired-OR logic is possible, which makes the logical capability greater than that of the DCFL circuit. In addition, this circuit has a larger driving capability. In this circuit, however, current flows through the source follower stage during the Hi level output, resulting in a larger power consumption. When the output terminal drops to the low level, charges are removed via the constant-current load composed of D-type FETs, making the driving capability low as compared with an active operation of pull-down FETs, such as a push-pull operation.
As described above, the DCFL circuit used as a basic circuit of conventional GaAs integrated circuits has the disadvantages of a small noise margin, a low load driving capability, and a low logic capability, which makes it impossible to make full use of the high-speed performance of GaAs MESFETs. There is also the problem that the yield drops significantly, when the threshold value varies as a result of process variations. Circuits proposed to solve those disadvantages of the DCFL circuit also have problems such as increasing the power consumption, and have not yet reached essential solutions.